A common method of designing an integrated circuit (IC) in a semiconductor design requires that an integrated circuit designer first provide a library of computer stored circuit cells and a behavioral circuit model describing the functionality of the integrated circuit. The circuit N cells typically include fundamental logic gates such as OR, NAND, NOR, AND, XOR, inverter, and like logical cells with an array of logic gate sizes. These cells also include sequential circuit elements such as latches and flip-flops for memory requirements. Generally, the library of computer stored circuit cells are generated by a layout designer manually. Because this process is time consuming and error prone, prior art methods and apparatus have been developed to automate this procedure.
FIG. 1 illustrates a methodology and apparatus implemented in these prior art systems. Typical prior art implementations include the Virtuoso Layout Synthesizer (LAS) tool from Cadence, the Auto Layout tool from Mentor Graphics, the Custom Cell Synthesizer (CCS) tool from MCC, and a Cadabra tool. The methodology implemented by prior art implementations will now be discussed in greater detail and with reference to FIG. 1.
A prior art implementation 10 includes step 12 whereby an external user provides a netlist and template. The netlist comprises a set of circuit primitives such as transistors and diodes, their sizes, and interconnections. The template describes the physical form of a standard circuit cell. The template may contain cell height, supply rail size, etc.
Next, in step 14 components of the netlist are placed in an appropriate location. Each of the components is then connected to one another in channel routing step 16. A resulting layout is subsequently compacted in step 18. Lastly, a layout designer is required to determine whether a resulting layout meets the template specified in initial step 12. Thus, in step 19, a layout designer must determine whether or not a cell height is met, whether there is proper density among the elements of the layout, and whether well height (abutment) constraints are met. Furthermore, if the layout designer determines that these constraints are not met, the layout designer must determine which parameters of the template specified in step 12 must be modified in order to generate a compliant layout. This often requires that the layout must be hand edited to meet these constraints. Each of the steps of the prior art implementation will now be discussed in greater detail.
In the first step 12, in which an external user provides a netlist and template, prior art implementation required that a physical netlist, and not a logical netlist, be provided. A physical netlist is one in which there is a one-to-one correspondence between devices specified in the netlist and the transistors implemented in a final layout. A physical netlist is different than a logical netlist which only specifies a function to be performed and is not optimized to meet the template requirements. Stated another way, a physical netlist requires user optimization before being provided to a next step in the prior art component placement step (step 14).
Because user optimization, or hand drafted optimization, is required, prior art implementations require a significant amount of time to simply generate one physical layout. In a slight improvement over the previously described prior art techniques, some prior art implementations provide semi-automatic means for translating logical netlists into physical netlists. However, even these slight improvements require user direction to specify a maximum transistor size. This user direction requirement again adds additional time to the layout process and introduces an increased likelihood in layout errors. As well, these prior art techniques have the undesired side effect of creating unnecessary interconnects between nodes guaranteed to be at a same electrical potential because of a manner in which a physical netlist is generated by such techniques.
In step 14 of the prior art implementation, the netlist components are placed in a two dimensional array to minimize certain cost metrics, where the cost metric is a quality indicator for the placement. Generally, a two-dimensional array is comprised of one row of N-type transistors and one row of P-type transistors. Typical cost metrics include wire length and cell height and width estimates. While a two-dimensional array is generally used, the two-dimensional array does not always give optimal results for each type of netlist. For example, because of a linear flow implemented within most prior art implementations, a cell placement selected during execution of step 14 is never modified automatically regardless of its effectiveness in satisfying a template requirement. Also, the prior art does not perform vertical alignment of transistors of the same type (P or N) in order to minimize wire length. Furthermore, prior art implementations tend to emphasize the minimization of interconnection lengths between the transistors forming the cell, but not the Channel Density (defined below). It should be noted that Channel Density should be minimized to minimize cell height. By minimizing interconnection length, prior art techniques fail to minimize a height of the cell.
In addition to the disadvantages delineated above, the method by which prior art implements step 14 component placement, also has several drawbacks. Included in these drawbacks is a method by which prior art places ties in the layout to satisfy latch-up rules. It should be noted that after transistors are placed, prior art implementations must place "merged ties" to connect a source or drain of the transistor to a power or ground source supply. Prior art implementations are only able to place ties at the certain specified locations and are not able to implement ties at optimal locations. Furthermore, it should be noted that even the requirement that the ties be placed at certain locations and provide certain connections between a transistor and a supply source utilizes only an ad hoc process which provides no optimization.
In addition to placing ties, prior art implementations also place ports during step 14. During the port placement step, an area in a cell is reserved to allow the cell to communicate with other cells by providing via sites or another form of interface. As with the tie placement operations, prior art implementations do not optimize placements of ports to provide maximum area utilization. Such port placement step is critical because if the port placement step is performed in an inefficient manner, block area routing will be adversely affected.
Additionally, in recent years, antenna diodes are being implemented by manual layout insertion to provide a contact from a metal layer to a Diffusion layer of a device for manufacturing purposes. This contact provides a path for charge generated in long metal lines during manufacturing to be dissipated without damaging a transistor gate or other circuit implemented on a semiconductor substrate. No prior art techniques currently available provide a method for automatically placing antenna diodes using computer software tools to create a cell layout.
In next step 16, interconnects between components are routed by the prior art implementations. Most prior art techniques implement a channel routing methodology which reflects an attempted solution to a classic layout optimization problem which has been studied extensively. Channel routing is a methodology implemented by prior art systems in which the channel is defined to be a region between a row of N-type transistors and P-type transistors. In performing routing between the two types of transistors, the channel routing implemented by prior art implementations fails to effectively utilize the region lying outside the channel between the two transistors. For example, the region on top of transistors could be used to route metal wires, and the region below the metal supply rails could be used for polysilicon connections. This is not done in the prior art. Additionally, in prior art implementations, the routing direction for each layer is predetermined and may not be modified during channel routing step 16. This fixed routing direction leads to one of the main disadvantages of using a channel router because it results in an increased number of contacts and vias that have adverse effects on area, electrical performance, and yield. Note that some prior art implementations augment channel routing with various ad hoc heuristic methods. However, these fail to overcome the fundamental disadvantage noted above.
In additional to channel routing, some prior art implementations implement an area routing technique. Area routing involves using an entire area of the layout to connect the components and does not limit it to a transistor channel. While the second prior art technique may provide more optimal results, prior art implementations have failed to provide a good solution for selectively increasing an area in which the routing may fail. Additionally, in prior art implementations of area routing, a routing direction is fixed for each layer. As with the channel routing implementations, this fixed directionality adversely affects the optimal nature of the routing operation.
After components are placed and interconnects are routed, layout compaction step 18 is implemented. While most prior art implementations include a layout compaction step, this step is not provided to optimize a well height and a cell height requirement. Some prior art implementations simply ignore the well height requirement problem, while other prior art implementations have attempted to provide well height support by implementing a fixed rectangular well region during a layout compaction step. However, this second technique is not optimal because it limits a height of each of the N-type and P-type transistors. If height requirements are not exceeded, a resulting circuit will not be optimal and will require a greater amount of area to implement. In addition to not adequately providing support for well height requirements, prior art implementations also fail to make efforts to compact a cell layout differently to obtain a narrower cell within a standard cell height.
In other prior art implementations, a two-dimensional compaction operation is implemented. In this process, both the height and the width of the cell are compacted simultaneously. While this methodology may provide a more optimal result, it is computationally intensive and therefore, is unable to optimize larger standard cells. Furthermore, an external user is unable to explore additional options because of the longer run time resulting from the computationally intensive procedure. Therefore, the user is often unable to explore additional placement and routing options which may prove to be optimal. Another drawback of the second implementation of a layout compaction step is that it requires a layout to be sub-divided into columns prior to the compaction step. While this procedure works for current placements of transistors, it is infeasible to use where the transistor placement is modified in a certain manner. For example, when the placement consists of both horizontal and vertical alignments of transistors, the two-dimensional compaction process will result in an erroneous compaction operation. Stated another way, the second two dimensional compaction methodology is not a general purpose compaction procedure.
Finally, after prior art implementations have been used to place components, route connections between the components, and compact that layout, a layout designer is required to inspect the layout and determine in an ad hoc manner whether the layout satisfies the template specified in step 12 and whether the layout is of good quality. For example, in step 19, the layout designer must determine whether or not cell and well height requirements are met, whether port placement is optimized, whether there is good density among the components, and whether or not an abutment requirement is met. Furthermore, the layout designer must determine whether or not the resulting layout satisfies all design rules. If any of these requirements are not satisfied, the layout designer must determine which input to the template must be modified to achieve certain goals. For example, such goals may include a smaller cell height or a cell which has different port placements. Furthermore, layout designers are unable to change routing direction or Tie Style unless they chose to do so manually using a layout editor. Lastly, it should be noted that in some prior art implementations, even steps 14, 16, and 18 are not automatic and the layout designer must come in at each point and make changes to control each tool. This hand editing step requires layout expertise and increases a latency related to a layout development time.
Therefore, it is desirable to have a methodology that may produce standard cell layouts in a fully automatic manner where the resulting layout complies with design rules and the required template, and has a good density.